Description: 我用过的verilog hdl写的SDRAM core源程序,经过测试应用-I used to write Verilog HDL source of SDRAM core, the test application Platform: |
Size: 27648 |
Author:于飞 |
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Description: Verilog HDL编写的串并转换。采用iout类型口。包含源文件和测试文件。用Modsim编译。-Verilog HDL Series and the preparation of the conversion. I used iout types. Includes source and test papers. Modsim compiler used. Platform: |
Size: 1024 |
Author:曹光明 |
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Description: 24C01A的Verilog HDL仿真代码，用于I2C接口模块的测试，由北京邮电大学《VerilogHDL设计与EDA技术基础》教师编写-24C01A simulation of Verilog HDL code for the I2C interface module of the test, by the Beijing University of Posts and Telecommunications VerilogHDL design and EDA technology infrastructure Teacher preparation Platform: |
Size: 1024 |
Author:emulous |
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Description: 三位全加器的源代码，和测试代码，用Verilog HDL实现的！-The three full adder of the source code, and test code, using Verilog HDL to achieve! Platform: |
Size: 35840 |
Author:陈吉成 |
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Description: 有实验结果,用MOSIN6编写的,是Verilog HDL语言实现的.
练习三 利用条件语句实现计数分频时序电路
实验目的：
1. 掌握条件语句在简单时序模块设计中的使用；
2. 学习在Verilog模块中应用计数器；
3. 学习测试模块的编写、综合和不同层次的仿真。
练习四 阻塞赋值与非阻塞赋值的区别
实验目的：
1． 通过实验，掌握阻塞赋值与非阻塞赋值的概念和区别；
2． 了解阻塞赋值与非阻塞赋值的不同使用场合；
3． 学习测试模块的编写、综合和不同层次的仿真。
-The experimental results are used to prepare MOSIN6 is achieved Verilog HDL language. Practice the use of conditional statements to achieve the three sub-frequency timing circuit count experimental purposes: 1. Have conditional statements in the simple timing of the use of modular design 2. Learning modules in the Verilog Application of counter 3. to learn the preparation of the test module, integrated and different levels of simulation. Practicing the four blocking assignment with the distinction between non-blocking assignment experimental purposes: 1. Through experiments, hands blocking assignment with the concept of non-blocking assignment and distinction 2. Understanding of blocking and nonblocking assignment assignment using different occasions 3. Test the preparation of learning modules, integrated and different levels of simulation. Platform: |
Size: 15360 |
Author:盼盼 |
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Description: Verilog HDL的程式，上網找到SPI程式，
vspi.v這程式相當好用可用來接收與傳送SPI，並且寫了一個傳輸信號測試，spidatasent.v這程式就是傳送的資料，分別為00 66... 01 77...... 02 55這樣的資料，並透過MAX+PULS II軟體進行模擬，而最外層的程式是test_createspi.v！-Verilog HDL programs, Internet find SPI program, vspi.v this very useful program can be used to receive and send SPI, and wrote a transmission signal test, spidatasent.v this program is to send the information, namely, 00 66 ... 01 77 ...... 02 55 This information, and through the MAX+ PULS II software simulation, while the outermost layer of the program are test_createspi.v! Platform: |
Size: 145408 |
Author:Rick |
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Description: 比特序列传送模块
把输入的八位比特数据 做循环后每个比特输出 详细请看英文描述-• To create Verilog-HDL modules written in the RTL style appropriate for both simulation and synthesis, for the various component parts of an Asynchronous Serial Data Transmitter.
• To verify the correct behaviour of each component part by means of simulation.
• To construct a top-level module corresponding to the Asynchronous Serial Data Transmitter, making use of the component parts developed above, and any additional behavioural elements which may be required.
• To verify the correct operation of the top-level design by means of simulation using a Verilog-HDL test-fixture.
• To automatically create a hierarchical logic diagram for the Asynchronous Serial Data Transmitter, generated using a Logic Synthesis tool. Platform: |
Size: 2048 |
Author:吴德昊 |
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Description: 介绍了如何编写正确且有效的vhdl/verilog hdl testbench,详细讲解了仿真测试程序的编写-Describes how to write correct and effective vhdl/verilog hdl testbench, explained in detail the preparation of the simulation test procedure Platform: |
Size: 5524480 |
Author:neo |
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Description: this Code is in verilog HDL.
This Code is for piplined processor with 4 opcode.
this will work in three cycle latch, decode and exicute..
test bench for xilinx ise is laos given
Platform: |
Size: 4096 |
Author:Yogesh PAtel |
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Description: 该测试程序用过Verilog HDL实现对PLL的分频，既频率管理功能-The Verilog HDL test procedure used to achieve the sub PLL frequency, only the frequency management function Platform: |
Size: 3072 |
Author:Henin Lu |
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Description: IEEE 2001 verilog 标准 ,详细讲述了 业内 公认的 VERILOG 标准 ,-The Verilog¤ Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEE
Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a
standard textual format for a variety of design tools, including verification simulation, timing analysis, test
analysis, and synthesis. It is because of these rich features that Verilog has been accepted to be the language
of choice by an overwhelming number of IC designers.
Platform: |
Size: 2200576 |
Author:adam |
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